View CXP851P16_4623982.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

?1 CXP851P16 e94332a18-ps cmos 8-bit single chip microcomputer sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 64 pin sdip (plastic) 64 pin qfp (plastic) description the CXP851P16 are highly integrated micro- computers composed of a 8-bit cpu, prom, ram, and i/o ports. these chips feature many other high- performance circuits in a single-chip cmos design, including an a/d converter, serial interface, timer/counter, time-base timer, vector interrupt, on- screen display function, i 2 c bus interface, pwm generator, remote control receiver, hsync counter, power supply frequency counter, and watchdog timer. also this ic provides power-on reset and sleep functions. the designers have ensured low power consumption for these powerful microcomputers. the CXP851P16 is the on-chip prom version of the cxp85116 with on-chip mask rom, providing the function of being able to write directly into the program. furthermore, because of the osd character rom can also be written directly into, it is suitable for evaluation use during system development and for small quantity production. structure silicon gate cmos ic features a wide instruction set (213 instructions) which cover various types of data. ?16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction minimum instruction cycle during operation 1s/4mhz incorporated prom capacity 16k bytes (for program) 3k bytes (for osd) incorporated ram capacity 352 bytes peripheral functions ?on-screen display function 12 16 dots, 128 types 4 lines of 21 characters (5 or more lines possible) double scanning mode supported includes jitter elimination circuit ?i 2 c bus interface ?pwm output 14-bits, 1 channel 6-bits, 8 channels ?remote control receiving circuit 8-bit pulse measuring counter, 6-stage fifo ?a/d converter 4-bit, 4-channel, successive approximation method (conversion time of 40s/4mhz) ?hsync counter ?power supply frequency counter ?watchdog timer ?8-bit synchronized serial i/o ?8-bit timer, 8-bit timer/counter, 19-bit time-base timer interruption 14 factors, 14 vectors, multiple interrupt possible standby mode sleep/stop package 64-pin plastic sdip/qfp perchase of sony's i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specifications as defined by philips.
?2 CXP851P16 on screen display serial i/o timer/counter remocon fifo hsync counter ac timer a/d converter i 2 c interface unit watch dog timer 14bit pwm 6 bit pwm 8ch clock gen./ system control ram 352 bytes spc700 cpu core prom 16k bytes prescaler/ time base timer port a port b port c port d port e port f 2 2 v ss v dd mp xtal extal rst pf0/pwm0 to pf7/pwm7 interrupt controller pe6/pwm pa0 to pa7 pb0 to pb7 pc0 to pc7 pd0 to pd7 pe0 to pe5 pe6 to pe7 pf0 to pf7 xlc b r blk hsync vsync pd3/si pd2/so pd1/sck pd7/ec pe7/to pd6/rmc pd4/hsi pd5/aci pe2/an0 to pe5/an3 pf4/scl0 pf5/scl1 pf6/sda0 pf7/sda1 pe0/int0 pe1/int1 pd0/int2 prom 3k bites g vpp exlc block diagram
3 CXP851P16 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 ec/pd7 rmc/pd6 aci/pd5 hsi/pd4 si/pd3 so/pd2 sck/pd1 v ss v dd vpp v ss mp pf0/pwm0 pf1/pwm1 pf2/pwm2 pf3/pwm3 pf4/pwm4/scl0 pf5/pwm5/scl1 pf6/pwm6/sda0 pf7/pwm7/sda1 blk r g b vsync hsync exlc xlc pe0/int0 pe1/int1 pe2/an0 pe3/an1 pe4/an2 pe5/an3 pe6/pwm pe7/to rst extal xtal pd0/int2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 1 pa1 pa0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 ec/pd7 pf3/pwm3 pf4/pwm4/scl0 pf5/pwm5/scl1 pf6/pwm6/sda0 pf7/pwm7/sda1 blk r g b vsync hsync exlc xlc pe0/int0 pe1/int1 pe2/an0 pe3/an1 pe4/an2 pe5/an3 rmc/pd6 aci/pd5 hsi/pd4 si/pd3 so/pd2 sck/pd1 v ss int2/pd0 xtal extal rst to/pe7 pwm/pe6 pa2 pa3 pa4 pa5 pa6 pa7 v ss v dd vpp mp pf0/pwm0 pf1/pwm1 pf2/pwm2 29 note) 1. vpp (pin 63) is always connected to v dd . 2. vss (pins 32 and 62) are both connected to gnd. 3. mp (pin 61) is always connected to gnd. note) 1. vpp (pin 56) is always connected to v dd . 2. vss (pins 26 and 58) are both connected to gnd. 3. mp (pin 55) is always connected to gnd. pin configuration (top view)
4 CXP851P16 (port a) single bit selectable 8-bit port. (8 lines) (port b) single bit selectable 8-bit port. (8 lines) (port c) single bit selectable 8-bit port. (8 lines) (port d) single bit selectable 8-bit port. 12ma sink current drive possible. (8 lines) (port e) 8-bit port, lower 6 bits for input, upper 2 bits for output. (8 lines) (port f) 8-bit output port with large current (12ma) n-ch open drain output. lower 4 bits middle voltage tolerance (12v), upper 4 bits 5v suppression. (8 lines) crt display 4-bit output pin. crt display horizontal synchronization signal input pin. crt display vertical synchronization signal input pin. pin description symbol pa0 to pa7 pb0 to pb7 pc0 to pc7 pd0/int2 pd1/sck pd2/so pd3/si pd4/hsi pd5/aci pd6/rmc pd7/ec pe0/int0 pe1/int1 pe2/an0 to pe5/an3 pe6/pwm pe7/to pf0/pwm0 to pf3/pwm3 pf4/pwm4/ scl0 pf5/pwm5/ scl1 pf6/pwm6/ sda0 pf7/pwm7/ sda1 r, g, b, blk hsync vsync i/o i/o i/o i/o/input i/o/i/o i/o/output i/o/input i/o/input i/o/input i/o/input i/o/input input/input input/input output/output output/output output/output output/output/ i/o output/output/ i/o output input input i/o description input pin for external interrupt request. active on falling edge. serial clock pin. serial data output pin. serial data input pin. hsync counter input pin. power supply frequency counter input pin. remote control receiver circuit input pin. external event timer/counter input pin. input pin for external interrupt request. active on falling edge. (2 lines) analog input pin for a/d converter. (4 lines) 14-bit pwm output pin. (cmos output) square wave output for timer 1. (50% duty cycle) 6-bit pwm output pin. (8 lines) i 2 c bus interface transfer clock input/output pin. i 2 c bus interface transfer data input/output pin.
5 CXP851P16 symbol exlc xlc extal xtal rst mp v dd vpp vss input output input output i/o input crt display clock oscillator input/output pin. oscillator frequency is determined by external l, c circuit. system clock oscillator crystal connection pin. when using an external clock, input to extal pin and leave xtal pin open. "l" level active system reset. this pin also acts as an input/output pin during power up. while internal power-on reset function is taking place a "l" level is output. (mask option) microprocessor mode input pin. must be connected to gnd. positive power supply pin. positive power supply pin for on-chip prom writing. please connect to v dd for normal operation. gnd. both vss pins should be connected to common gnd. i/o description
6 CXP851P16 data bus rd (port d) aa ip aa aa aaaaa aaaaa port d direction aaaaa aaaaa port d data high current 12ma schmitt input sck only sck or so output enable data bus rd (port a, b, c) aa aa ip aa aa input protection circuit aaaa aaaa port a data port b data port c data aaaa aaaa port a direction port b direction port c direction data bus rd (port d) a a ip aa aaaa aaaa port d direction aaaa aaaa port d data high current 12ma int2, si, hsi, aci, rmc, ec schmitt input port d 2 pins pd1/sck pd2/so input/output circuit formats for pins port a port b port c port d 24 pins 6 pins hi-z hi-z hi-z pin when reset circuit format pa0 to pa7 pb0 to pb7 pc0 to pc7 pd0/int2 pd3/si pd4/hsi pd5/aci pd6/rmc pd7/ec
7 CXP851P16 a a aa ip rd (port e) data bus schmitt input (to interrupt circuit) aa aa a a ip input multiplexer to a/d converter rd (port e) data bus to, pwm aaaa aaaa port selection aaaa aaaa aa aa port e data port e 2 pins 4 pins 2 pins pe0/int0 pe1/int1 port e port e h level hi-z hi-z pe2/an0 to pe5/an3 pe6/pwm pe7/to scl, sda aaaa aaaa port selection aaaa aaaa aa aa port f data pwm i 2 c output enable aa aa ip schmitt input scl, sda (to i 2 c circuit) to other i 2 c pins bus sw pwm aaaaa aaaaa port selection aaaaa aaaaa aa aa port f data middle tension proof 12v high current 12ma port f port f 4 pins 4 pins pf4/pwm4/ scl0 pf5/pwm5/ scl1 pf6/pwm6/ sda0 pf7/pwm7/ sda1 hi-z hi-z pf0/pwm0 to pf3/pwm3 pin when reset circuit format
8 CXP851P16 4 pins 2 pins hi-z oscillation halted blk r g b exlc xlc aa blk, r, g, b to output polarity register writing data to port register brings output from high impedance to active aaaa aaaa output polarity 2 pins hi-z hsync vsync hsync vsync aa aa a ip schmitt input aaa aaa input polarity oscillator control aa aa exlc aa aa aa aa ip crt display clock a a ip xlc 2 pins 1 pin rst oscillation l level extal xtal aa aa a a ip aa aa extal xtal diagram indicates equivalent circuit during oscillation feedback resistor is disconnected during stop aa aa schmitt input pull-up resistor from power-on reset circuit (mask option) mask option op 1 pin mp hi-z a a aa ip cpu mode pin when reset circuit format
9 CXP851P16 ? 1) v in and v out should not exceed v dd + 0.3v. ? 2) the high current operation transistors are the n-ch transistors of the pd and pf0 to pf3 ports. note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should better take place under the recommended operating conditions. exceeding those conditions may adversely affect the reliability of the lsi. v dd vpp v in v out v outp i oh i oh i ol i olc i ol topr tstg p d 0.3 to +7.0 0.3 to +13.0 0.3 to +7.0 ? 1 0.3 to +7.0 ? 1 0.3 to +15.0 5 50 15 20 130 10 to +75 55 to +150 1000 600 v v v v v ma ma ma ma ma c c mw mw incorporated prom pins pf0 to pf3 total of all output pins excludes large current output large current output ? 2 total of all output pins sdip qfp symbol ratings unit remarks absolute maximum ratings (vss = 0v) supply voltage high level input voltage low level input voltage operating temperature 5.5 5.5 5.5 v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.4 +75 v v v v v v v v v v c item symbol min. max. unit remarks 4.5 3.5 2.5 0.7v dd 0.8v dd v dd 0.4 0 0 0.3 10 vpp v ih v ihs v ihex v il v ils v ilex topr guaranteed range during operation guaranteed range for low speed data ? 1 guaranteed data hold operation range during stop ? 5 i 2 c schmitt input included ? 2 cmos schmitt input ? 3 extal pin ? 4 i 2 c schmitt input included ? 2 cmos schmitt input ? 3 extal pin ? 4 v dd ? 1) rating for 1/16 frequency mode and sleep mode. ? 2) normal input port (all pins of pa, pb, pc, pe2 to pe5), pf4 tp pf7, and mp pins. ? 3) includes pd0/int2, pd1/sck, pd2, pd3/si, pd4/hsi, pd5/aci, pd6/rmc, pd7/ec, pe0/int0, pe1/int1, hsync, vsync, rst pins. ? 4) it specifies only when the external clock is input. ? 5) vpp and v dd should be set to a same voltage. recommended operation conditions (vss = 0v) item vpp = v dd supply voltage input voltage output voltage medium voltage tolerance output voltage high level output current high level total output current low level output current low level total output current operating temperature strage temperature allowable power dissipation
10 CXP851P16 v dd = 4.5v, i oh = 0.5ma v dd = 4.5v, i oh = 1.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 3.0ma v dd = 4.5v, i ol = 4.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 4.5v, i ol = 12.0ma high level output voltage low level output voltage input current input/output leak current open drain output leak current (n-ch tr off case) i 2 c bus switch connection impedance (output tr off case) supply current input capacitance 4.0 3.5 10 0.7 10 3 30 20 a pf 25 50 10 120 ma ma a a ? 0.4 0.6 1.5 0.4 0.6 40 40 400 10 v v v v v a a a a 0.5 0.5 1.5 v v pa to pd, pe6, pe7, r, g, b, blk pa to pd, pe6, pe7, r, g, b, blk, pf0 to pf3, rst pd, pf0 to pf3 pf4 to pf7 (scl0, scl1, sda0, sda1) extal rst pa to pe, hsync, vsync, r, g, b, blk, mp pf0 to pf3 pf4 to pf7 scl0: scl1 sda0: sda1 v dd = 5.5v, v il = 0.4v v dd = 5.5v v i = 0, 5.5v v dd = 5.5v, v oh = 12.0v v dd = 5.5v, v oh = 5.5v v dd = 4.5v v scl0 = v scl1 = 2.25v v sda0 = v sda1 = 2.25v v dd ? operating mode ? (1/2 clock rate) 4mhz crystal oscillator (c 1 = c 2 = 22pf) all output pins open stop mode sleep mode pins other than v dd and vss 1mhz clock 0v other than the measure pins item symbol pin condition min. typ. max. unit v oh v ol i iz i loh r bs i dd i ddsl i ddst c in i ihe i ihl i ilr dc characteristics (ta = 10 to +75 c, vss = 0v) ? rating applies only if osd oscillator is haited.
11 CXP851P16 ac characteristics (1) clock timing ? tsys indicates three values according to the contents of the clock control register (address: 00fe h ) upper 2 bits (cpu clock selection). t sys (ns) = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") system clock frequency system clock input pulse width system clock rise and fall times event counter input clock pulse width event counter input clock rise and fall times f c t xl , t xh t cr , t cf t eh , t el t er , t ef xtal extal extal extal ec ec mhz ns ns ns ms item symbol pin condition min. max. unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive fig. 3 fig. 3 4.5 200 20 3.5 100 t sys + 50 ? (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) fig. 1. clock timing extal t xh t xl t cf t cr 0.4v v dd 0.4v 1/fc fig, 2. clock applied condition aaaaa a aaa a aaaaa aaaaa a aaa a aaaaa crystal oscillator ceramic oscillator extal xtal external clock extal xtal open c 1 c 2 fig. 3. event count clock timing ec t eh t el t ef t er 0.2v dd 0.8v dd
12 CXP851P16 (2) serial transfer (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) item sck cycle time t kcy sck input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode 1000 8000/fc 400 4000/fc 50 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns sck si si so t kh t kl t sik t ksi t kso sck high and low level widths si input set up time (against sck ) si input hold time (against sck ) sck so delay time symbol pin condition min. max. unit note) the load of sck output mode and so output delay time is 50pf + 1ttl. fig. 4. serial transfer timing 0.2v dd 0.8v dd t kl t kh so t kcy t sik t ksi 0.2v dd 0.8v dd t kso 0.2v dd 0.8v dd output data input data si sck
13 CXP851P16 external interrupt high and low level widths reset input low level width int0 to int2 rst 1 8/fc s s item symbol pin condition min. max. unit t ih t il t rsl power supply rise time power supply cut-off time t r t off v dd power-on reset repetitive power-on 0.05 1 50 ms ms (3) interrupt, reset input (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) (4) power-on reset power-on reset ? (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) 0.2v dd 0.8v dd t ih t il int0 to int2 (falling edge) 0.2v 0.2v 4.5v v dd t r t off the power supply should rise smoothly. fig. 5. interrupt input timing t rsl 0.2v dd rst fig. 6. rst input timing fig. 7. power-on reset item symbol pin condition min. max. unit ? specifies only when power-on reset function is selected.
14 CXP851P16 resolution linearity error zero transition voltage full-scale transition voltage conversion time sampling time analog input voltage v zt ? 1 v ft ? 2 t conv t samp v ian an0 to an3 ta = 25 c v dd = 5.0v vss = 0v 10 4370 160/fc 12/fc 0 160 4530 4 1 320 4690 v dd bits lsb mv mv s s v item symbol pin condition min. typ. max. unit (5) a/d converter characteristics (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) linearity error v zt v ft analog input f h e h 1 h 0 h digital conversion value fig. 8. definitions for a/d converter terms ? 1) v zt : indicates the value that digital conversion value changes from 00 h to 01 h and vice versa. ? 2) v ft : indicates the value that digital conversion value changes from e h to f h and vice versa. note) for 4-bit conversion, correction of the upper 5 bits a/d data register (add: address 00f5 h ) into 4 bit data is defined according to the following program example. (a/d converter program example) mov a, add ; acc conversion data lsr a ; logical shift right (4 times) lsr a ; lsr a ; lsr a ; adc a, #00h ; carry addition (if ad3 is 1, data is incremented) cmp a, #10h ; bne adc_skip ; mov a, #0fh ; adc_skip:
15 CXP851P16 (6) i 2 c bus timing (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) item scl clock frequency bus free time before starting transfer hold time for starting transfer clock low level width clock high level width set-up time for repetitive transfers data hold time data set-up time sda, scl rise time sda, scl fall time set-up time for transfer completion f slc t buf t hd; sta t low t high t su; sta t hd; dat t su; dat t r t f t su; sto scl sda, scl sda, scl scl scl sda, scl sda, scl sda, scl sda, scl sda, scl sda, scl 0 4.7 4.0 4.7 4.0 4.7 0 ? 250 4.7 100 1 300 khz s s s s s s ns s ns s symbol pin condition min. max. unit ? since scl rise time (max: 300ns) is not considered part of data hold time, allow at least 300ns. fig. 9. i 2 c bus transfer data timing p st t su; sto t su; sta t hd; sta t su; dat t high t hd; dat t f t r t low t hd; sta s p t buf sda scl fig. 10. i 2 c device recommended circuit i 2 c device i 2 c device r s r s r s r s r p r p sda0 (or sda1) scl0 (or scl1) a pull-up resistor must be connected to sda0 (or sda1), and scl0 (or scl1). the sda0 (or sda1) and scl0 (or scl1) series resistance (rs = 300 ? or less) can be used to reduce spike noise caused by crt flashover.
16 CXP851P16 (7) osd (on screen display) timing (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) item osd clock frequency hsync pulse width hsync afterwrite rise and fall times vsync afterwrite rise and fall times f osc t hwd t hcg t vcg exlc xlc hsync hsync vsync fig. 12 fig. 11 fig. 11 fig. 11 4 1.2 13 200 1.0 mhz s ns s symbol pin condition unit min. max. fig. 11. osd timing 0.8v dd 0.2v dd t hcg t hwd hsync for opol register (01fb h ) bit 5 at "0" 0.8v dd 0.2v dd t vcg vsync for opol register (01fb h ) bit 4 at "0" fig. 12. lc oscillator circuit connection l c 2 c 1 exlc xlc
17 CXP851P16 4.00 4.19 4.00 4.19 4.00 4.19 4.00 4.19 supplement fig. 13. recommended oscillation circuit c 2 c 1 aaaaa a aaa a aaaaa extal xtal rd aaaaa a aaa a aaaaa extal xtal rd (i) aaaaa a aaa a aaaaa extal xtal c 1 c 2 rd xtal (ii) manufacturer murata mfg co., ltd. kinseki ltd. model csa4.00mg csa4.19mg cst4.00mgw ? cst4.19mgw ? hc-49/u03 hc49/u (-s) fc (mhz) 30 15 30 15 0 0 c 1 (pf) c 2 (pf) rd ( ? ) circuit example (i) (ii) (i) 22 18 22 18 0 ? indicates types with on-chip grounding capacitors (c 1 and c 2 ). selection guide river eletec co., ltd. option item package prom capacitance reset pin pull-up resistor power-on reset circuit font data 64-pin plastic sdip/qfp 12k/16k bytes existent/non-existent existent/non-existent user specified 64-pin plastic sdip prom 16k bytes existent existent user specified (prom) ? 64-pin plastic qfp prom 16k bytes existent existent user specified (prom) ? mask version CXP851P16as-1- CXP851P16aq-1- ? the font data for the one-time prom version is operated in the same way as the program writing.
18 CXP851P16 fig. 14. characteristic curves 100 10 0 l inductance (h) parameter curve for osd oscillator l vs. c (analytically calculated value) 50 100 c 1 , c 2 capacitance (pf) 5.0mhz 6.5mhz 13.0mhz 23 v dd supply voltage (v) 1 1 16 sleep mode 456 0.1 10 15 1 4 1 2 23 fc system clock (mhz) i dd supply current (ma) i dd vs. fc (v dd = 5v, ta = 25 c, typical) 45 6 0 14 sleep mode 1 13 12 11 10 9 8 7 6 5 4 3 2 1 frequency mode 1 2 1 4 1 16 1 frequency mode frequency mode i dd supply current (ma) frequency mode frequency mode frequency mode i dd vs. v dd (fc = 4mhz, ta = 25 c, typical) f osc = c = c 1 //c 2 1 2 lc
19 CXP851P16 package outline unit: mm 64pin sdip (plastic) min 0.5 min 3.0 4.75 ?0.1 0.9 0.15 0.5 0.1 0.25 ?0.05 + 0.1 17.1 ?0.1 19.05 132 33 64 1.778 57.6 ?0.1 + 0.4 package material lead treatment lead material package mass epoxy resin 42/copper alloy sony code eiaj code jedec code sdip-64p-01 p-sdip64-17.1x57.6-1.778 solder plating 8.6g + 0.3 + 0.3 0? to 15? package structure 64pin sdip (plastic) min 0.5 min 3.0 4.75 0.1 0.9 0.15 0.5 0.1 0.25 0.05 + 0.1 17.1 0.1 19.05 132 33 64 1.778 57.6 0.1 + 0.4 package material lead treatment lead material package mass epoxy resin 42/copper alloy sony code eiaj code jedec code sdip-64p-01 p-sdip64-17.1x57.6-1.778 solder plating 8.6g + 0.3 + 0.3 0 ? to 15 ? package structure lead specifications item lead material alloy 42 lead treatment sn-bi 2.5% lead treatment thickness 5-18 m spec.
20 CXP851P16 package outline unit: mm sony code eiaj code jedec code 23.9 0.4 20.0 0.1 0.4 0.1 + 0.15 14.0 0.1 1 19 20 32 33 51 52 64 0.15 0.05 + 0.1 2.75 0.15 16.3 0.1 0.05 + 0.2 0.8 0.2 m 0.2 0.15 + 0.4 17.9 0.4 + 0.4 + 0.35 64pin qfp (plastic) qfp-64p-l01 p-qfp64-14x20-1.0 package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy package structure 1.5g 1.0 0 ? to10 ? sony code eiaj code jedec code 23.9 0.4 20.0 0.1 0.4 0.1 + 0.15 14.0 0.1 1 19 20 32 33 51 52 64 0.15 0.05 + 0.1 2.75 0.15 16.3 0.1 0.05 + 0.2 0.8 0.2 m 0.2 0.15 + 0.4 17.9 0.4 + 0.4 + 0.35 64pin qfp (plastic) qfp-64p-l01 p-qfp64-14x20-1.0 package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy package structure 1.5g 1.0 0 ? to10 ? lead specifications item lead material alloy 42 lead treatment sn-bi 2.5% lead treatment thickness 5-18 m spec. sony corporation

▲Up To Search▲

Price & Availability of CXP851P16

	To Download CXP851P16 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .